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| HM6207H Series 262,144-word x 1-bit High Speed CMOS Static RAM Features * Single 5 V supply and high density 24-pin package * High speed Access time: 25/35/45 ns (max) * Low power Operation: 300 mW (typ) Standby: 100 W (typ) 30 W (typ) (L-version) * Completely static memory required, no clock or timing strobe required * Equal access and cycle time * Directly TTL compatible, all inputs and outputs * Battery backup operation capability (L-version) Ordering Information Type No. HM6207HP-25 HM6207HP-35 HM6207HP-45 HM6207HLP-25 HM6207HLP-35 HM6207HLP-45 HM6207HJP-25 HM6207HJP-35 HM6207HJP-45 HM6207HLJP-25 HM6207HLJP-35 HM6207HLJP-45 Access Time 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 300-mil 24-pin SOJ (CP-24D) Package 300-mil 24-pin plastic DIP (DP-24NC) HM6207H Series Pin Arrangement A17 A0 A1 A2 A3 A4 A5 A6 A7 Dout WE VSS 1 2 3 4 5 6 7 8 9 10 11 12 (Top view) 24 23 22 21 20 19 18 17 16 15 14 13 VCC A16 A15 A14 A13 A12 A11 A10 A9 A8 Din CS Pin Description Pin Name A0-AI7 Din Dout CS WE VCC VSS Function Address Data input Data output Chip select Write enable Power supply Ground 2 HM6207H Series Block Diagram A15 A16 A17 A0 A1 A2 A3 A4 Din Row decoder Memory array 256 x 1024 VCC VSS Column I/O Column decoder Dout CS WE A9 A14 A13 A12A11 A10 A8 A7 A6 A5 Function Table CS H L L WE x H L Mode Not selected Read Write VCC Current I/O Pin I SB , I SB1 lCC I CC High-Z Dout High-Z Ref. Cycle -- Read cycle Write cycle Note: x = Don't care. Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Power dissipation Operating temperature range Storage temperature range Storage temperature range under bias Note: Symbol Vin PT Topr Tstg Tbias Value -0.5 to +7.0 1.0 0 to +70 -55 to +125 -10 to +85 *1 Unit V W C C C 1. Vin min = -2.5 V for pulse width < 10 ns. 3 HM6207H Series Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VCC VSS Input high (logic 1) voltage Input low (logic 0) voltage Note: VIH VIL Min 4.5 0 2.2 -0.5 *1 Typ 5.0 0 -- Max 5.5 0 6.0 0.8 Unit V V V V -- 1. VIL min = -2.0 V for pulse width 10 ns. DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM6207H-25 Parameter Input leakage current Output leakage current Operating power supply current Symbol Min I LI I LO lCC I CC1 -- -- -- -- Typ -- -- 60 40 *1 HM6207H-35/45 Max Min Typ*1 Max Unit Test Conditions 2.0 -- -- -- 50 40 2.0 A VCC = Max, Vin = VSS to V CC CS = VIH, VI/O = VSS to V CC CS = VIL, II/O = 0 mA, min cycle, duty = 100% CS = VIL, lI/O = 0 mA, t cycle = 50 ns, duty = 100% CS = VIH, min cycle CS V CC - 0.2 V, 0 V Vin < 0.2, or Vin V CC - 0.2 V 10.0 -- 120 -- 80 -- 10.0 A 100 mA 80 mA Standby power supply current I SB Standby power supply current (1) I SB1 -- -- 20 0.02 40 2.0 -- -- 15 0.02 30 2.0 mA mA LVersion Output low voltage Output high voltage Note: VOL VOH -- -- 2.4 0.006 0.1 -- -- 0.4 -- -- -- 2.4 0.006 0.1 -- -- 0.4 -- V V I OL = 8 mA I OH = -4.0 mA 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. Capacitance (Ta = 25C, f = 1 MHz)*1 Parameter Input capacitance Output capacitance Note: Symbol Cin Cout Min -- -- Max 6 10 Unit pF pF Test Conditions Vin = 0 V Vout = 0 V 1. This parameter is sampled and is not 100% tested. 4 HM6207H Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10% unless otherwise noted) Test Conditions * * * * Input pulse levels: VSS to 3.0 V Input and output timing reference levels: 1.5 V Input rise and fall time: 5 ns Output load: See figures +5V 480 +5V 480 Dout 255 Dout 255 30 pF *1 5 pF *1 Output load (A) Output load (B) (tHZ , tLZ, tWZ, and tOW) Note: 1. Including scope and jig Read Cycle HM6207H-25 Parameter Read cycle time Address access time Chip select access time Output hold from address change Chip selection to output in low-Z Chip deselection to output in high-Z Note: Symbol t RC t AA t ACS t OH t LZ *1 *1 HM6207H-35 Min 35 -- -- 5 5 0 Max -- 35 35 -- -- 20 HM6207H-45 Min 45 -- -- 5 5 0 Max -- 45 45 -- -- 20 Unit ns ns ns ns ns ns Min 25 -- -- 5 5 0 Max -- 25 25 -- -- 15 t HZ 1. Transition is measured 200 mV from steady-state voltage with Load (B). These parameters are sampled and not 100% tested. 5 HM6207H Series Read Timing Waveform (1) tRC Address tAA tOH Dout Notes: 1. WE is high for read cycle. 2. Device is continuously selected, CS = VIL. Valid Data tOH Read Timing Waveform (2) tRC CS tACS tLZ Dout High impedance Valid Data High impedance tHZ Notes: 1. WE is high for read cycle. 2. Address valid prior to coincident with CS transition low. 6 HM6207H Series Write Cycle HM6207H-25 Parameter Write cycle time Chip selection to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time Symbol t WC t CW t AW t AS t WP t WR t DW t DH *1 *1 HM6207H-35 Min 35 30 30 0 25 3 20 0 0 0 Max -- -- -- -- -- -- -- -- 20 -- HM6207H-45 Min 45 40 40 0 25 3 20 0 0 0 Max -- -- -- -- -- -- -- -- 25 -- Unit ns ns ns ns ns ns ns ns ns ns Min 25 20 20 0 20 3 15 0 0 0 Max -- -- -- -- -- -- -- -- 15 -- Write enabled to output in high-Z t WZ Output active from end of write Note: t OW 1. Transition is measured 200 mV from high-impedance voltage with Load (B). This parameter is sampled and is not 100% tested. Write Timing Waveform (1) (WE Controlled) tWC Address tCW CS tAW tAS WE tDW tDH tWP tWR Din tWZ Dout Valid Data tOW High impedance 7 HM6207H Series Write Timing Waveform (2) (CE Controlled) tWC Address tAS CS tAW tWP WE tDW Din tWZ Dout Data undefined High impedance Notes: 1. A write occurs during the overlap of a low CS and a low WE. 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. If the CS low transition occurs simultaneously with the WE low transition, the output buffers remain in a high impedance state. 4. Dout has the same phase as write data in this write cycle, if tWR is long enough. Valid Data tDH tWR tCW 8 HM6207H Series Low VCC Data Retention Characteristics (Ta = 0 to +70C) These characteristics are guaranteed for the L-version only. Parameter VCC for data retention Symbol VDR Min 2.0 Typ -- Max -- Unit V Test Conditions CS V CC - 0.2 V, Vin V CC - 0.2 V, or 0 V Vin 0.2 V Data retention current I CCDR -- 0 5 2 -- -- 50*1 -- -- A ns ms Chip deselect to data retention time t CDR Operation recovery time Note: 1. VCC = 3.0 V tR Low V CC Data Retention Timing Waveform Data retention mode 4.5 V tCDR 2.2 V VDR CS 0V CS VCC - 0.2 V tR VCC 9 HM6207H Series Package Dimensions HM6207HP/HLP Series (DP-24NC) 29.88 30.48 Max Unit: mm 24 13 7.40 Max 7.10 1 1.14 1.27 Max 1.30 12 5.08 Max 7.62 0.51 Min 2.54 Min 2.54 0.25 0.48 0.10 0.25 - 0.05 0 - 15 + 0.11 HM6207HJP/HLJP Series (CP-24D) 15.63 16.00 Max 24 13 7.62 0.13 8.64 0.13 Unit: mm 1 0.74 12 3.50 0.26 0.21 2.40 + 0.24 - 1.30 Max 0.43 0.10 1.27 0.10 0.80 +0.25 -0.17 6.76 - 0.16 + 0.35 10 |
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